Design Verification Engineer (UVM, PCIe, Ethernet) | Onsite | San Jose, CA and Austin, TX | 6+ Years

Job Overview

Cohesive Technologies is hiring six Design Verification Engineers to join its Interface IP DV team. This is an onsite opportunity based in San Jose, CA and Austin, TX for experienced engineers who enjoy solving hard verification problems. You will work closely with architects, designers and vendors to confirm that every architecture requirement is met in the IP subsystems and interfaces being built, and you will validate correctness and performance across the full hardware and software stack.

Position

Design Verification Engineer (6 openings)

Location

San Jose, CA and Austin, TX

Work Model

Onsite

Employment Type

Full Time

Experience

6 to 12 years of design verification experience

About the Interface IP DV Team

The Interface IP DV team makes sure that the IP subsystems and interfaces inside the chip behave exactly as the architecture intends. The work spans high-speed interfaces such as PCIe and Ethernet, CPU subsystems built on ARC or ARM, low power peripherals and sensors. The team partners with architects, RTL designers, integration engineers, SoC DV teams and external IP vendors. This role calls for creativity, deep technical ability and the drive to take on complex verification challenges in a fast-paced startup environment.

Key Responsibilities of the Design Verification Engineer

End to End IP Subsystem Ownership

Take end to end ownership of one or more IP subsystems, including PCIe, Ethernet, CPU (ARC or ARM), low power peripherals and sensors. You will be the go-to verification owner for your subsystem from planning through sign-off.

Vendor IP Configuration and Handshake

Understand vendor IP configurations and manage the handshake between external vendors and the internal IP team so that requirements, configurations and deliverables stay aligned.

UVM and SystemVerilog Verification Environments

Develop and maintain UVM and SystemVerilog based verification environments that confirm functional correctness, performance and compliance with IP specifications.

Integration and SoC Collaboration

Collaborate with integration and SoC DV teams to validate that external IPs interact smoothly within the broader chip architecture.

Coverage Closure and Sign-Off

Drive coverage closure and sign-off by defining metrics, analyzing gaps and making sure verification is thorough across corner cases and stress scenarios.

Required Skills for the Design Verification Engineer Position

Design Verification Experience

6 to 12 years of hands-on design verification experience.

SystemVerilog and UVM

Hands-on experience with industry-standard verification methodologies like SystemVerilog and UVM, along with a clear understanding of how to build scalable and reusable testbenches.

Standard IP Interfaces and Protocols

Comfort working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI and AMBA, or ARM and ARC CPUs.

Problem Solving

You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

Ownership

You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

Cross-Functional Communication

You collaborate naturally with cross-functional teams, from RTL design to software and emulation, and you can communicate technical insights clearly.

Preferred Qualifications

Strong candidates may also have experience with:

• Handling vendors and integrating third-party IP and VIP
• UVM and SystemVerilog based verification of vendor IP

Why This Role Stands Out

This position gives you true ownership of critical interface IP in a startup setting where your decisions shape the quality of the final silicon. You will work on some of the most widely used protocols in the industry, influence verification strategy from the start and collaborate with experienced architects and designers. If you like being trusted with a subsystem and seeing it through to sign-off, this role offers that scope.

Who Should Apply

This opportunity suits Design Verification Engineers, IP Verification Engineers and Senior DV Engineers with 6 to 12 years of experience who have built UVM testbenches for interfaces such as PCIe, Ethernet or AXI. Candidates must be able to work onsite in San Jose, CA or Austin, TX.

Frequently Asked Questions

1. What is the job title for this opening?

The role is Design Verification Engineer on the Interface IP DV team.

2. How many openings are available?

There are six openings for this position.

3. Where are these positions located?

The positions are based in San Jose, CA and Austin, TX.

4. Is this role remote or hybrid?

No. This is an onsite role in San Jose, CA or Austin, TX.

5. What type of employment is this?

This is a full-time position.

6. How much experience is required?

Candidates should have 6 to 12 years of design verification experience.

7. Which IP subsystems will I work on?

You will own one or more subsystems such as PCIe, Ethernet, CPU (ARC or ARM), low power peripherals and sensors.

8. Which verification methodologies are required?

Hands-on experience with SystemVerilog and UVM is required, including building scalable and reusable testbenches.

9. Which protocols should I be familiar with?

Familiarity with PCIe, Ethernet, AXI and AMBA, or ARM and ARC CPUs is expected.

10. Will I work with external vendors?

Yes. You will understand vendor IP configurations and manage the handshake with the internal IP team.

11. Who will I collaborate with?

You will work with architects, RTL designers, vendors, integration teams, SoC DV teams, software and emulation teams.

12. What does coverage closure involve in this role?

You will define metrics, analyze coverage gaps and make sure verification covers corner cases and stress scenarios before sign-off.

13. What preferred experience makes a candidate stand out?

Experience handling vendors and integrating IP and VIP is a strong plus.

14. What kind of work environment should I expect?

Expect a fast-paced startup environment where engineers take ownership of projects with minimal direction.

15. How do I apply for this Design Verification Engineer role?

Send your resume to rishib@cohetech.com and mention the Design Verification Engineer role and your preferred location.

Ready to Apply

If you are a Design Verification Engineer with strong UVM and SystemVerilog skills and experience with PCIe, Ethernet or CPU subsystems, we would like to hear from you. Email your resume to rishib@cohetech.com and include your preferred location, San Jose, CA or Austin, TX.

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